MSP430F5529时钟详解
1、以后要配置时钟的地方到处都是。
2、打字好累，上传更累；
3、之后我会发布PDF版，有心的同学可以下载学习。
之前有一点漏说明了，先补充上
***************************************************************还有一个模块时钟源：MODOSC，产生MODCLK时钟源信号，一般只为闪存控制模块和ADC12模块提供服务。
该模块不被使用时自动关闭，任何模块对该时钟源提出使用要求时，MODOSC无需被使能即可响应该请求。430F5529中MODCLK为5MHZ。
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MSP430F5529有多个时钟源，而且很多模块其时钟源都是可以自由选择的。此外，由于一般情况下，系统功耗是和工作频率成正比的，因此有些时候通过选择较低频率的时钟源，在满足正常工作条件下，是可以有效降低功耗的。虽然函数库HAL_UCS.c/h，有完整的各个控制函数，但我觉得对于这一章还是对寄存器直接操作比较简单，因为函数太短、太多了。
3.1统一时钟系统（UCS）的简介
Unified Clock System，UCS。合理的配置时钟，可以达到平衡系统且降低功耗的目的。
MSPF5529时钟系统包含5个时钟源：
①LFXT1 外部低频振荡源，32.768KHZ，可以用作FLL的参照源；
②XT2 外部高频振荡源，4MHZ；
③VLO （Internal very low）内部低耗低频振荡源，典型为10KHZ，精度一般；
④REFO 内部低频参照源，32.768KHZ，常被用作锁相环FLL的基准频率，精度很高，不使用时不消耗电源，其设置往往要参考LPM模式的的设置；
⑤DCO （Internal digitally-controlled）内部数字控制振荡源，一般通过FLL来设置；（很有用，很重要，之后会详细讲）
通常使用3种时钟信号，它们都来自于上述5个信号源：
①ACLK （Auxiliary clock）辅助时钟，其时钟源可由软件控制从XT1、REFOC、VLO、DCO、DCOCLKDIV、XT2里面选取。其中DCOCLKDIV是由DCO经1、2、4、8、16或者32分频得到。注意，ACLK同样可以再次被1、2、4、8、16或者32分频。
②MCLK （Master clock）主时钟，其特性与ACLK一模一样。
③SMCLK （Subsystem master clock）子系统时钟，其特性与ACLK一模一样。
3.2 UCS的操作说明
开机上电时默认的时钟情况为（必须记清楚！！！！）：
ACLK：XT1（无效时，低频模式切换为REFO，其他情况切换为DCO）
MCLK：DCOCLKDIV
SMCLK：DCOCLKDIV
此外，FLL的参照源默认XT1；
如果连接XT1和XT2的引脚不进行PXSEL的设置，那么这两个时钟源都是无效的；
REFOCLK、VLOCLK、DCOCLK默认状态下是可用的；
系统稳定后，DCOCLK默认为2.097152MHZ，FLL默认2分频，则MCLK和SMCLK的频率都为1.048576MHZ。（实验三会提到如何计算）
另外，系统复位、系统工作模式LPM的选择都会对UCS有一定影响，这里限制太多，具体可参考TI官方资料UCS部分。LPM以及系统复位下章将会讲到。
关于操作说明的简单总结：（下面基本都是废话，了解即可）
①VLO的选择是最简单的，不需要顾及其它情况；
②REFO的选用，需要参考不同的工作模式，有多种限制；
③XT1和XT2特点相同。使用的时候，不仅要配置与其相连的引脚，还要配置电容，还要注意其本身工作在低频还是高频模式。而且，在不同工作模式下也有不同的要求；
④DCO作为数控振荡器，其频率的调节不仅可以通过自身设定，也可以通过FLL锁相环设定；
⑤FLL锁相环，是变换频率的灵活选择。它既可以设置基准频率，也可以选择分频数，还可以被直接关闭来实现降低功耗等目的；
⑥UCS系统带有时钟信号错误保护机制；
⑦对有严格时序要求的地方，要选择精度高的时钟源，并且做好FLL和DCO部分的调制设置；
⑧不同模式下（有些时钟源是禁止的）的时钟控制图：（只需用到的时候注意一下即可，查表）
3.3 UCS寄存器控制操作
共有10组16位读写寄存器，为UCSCTL0-UCSCTL9。同样支持字和字节操作，即UCSCTL0包括UCSCTL0_H和UCSCTL0_L。
注：凡是标记“Reserved”的位，如果没有特意声明，则读回时都按0处理。
UCSCTL0
DCO ：DCO频拍选择。选择DCO的频拍并在FLL运行期间（因MOD位的变化）自动调整。。DCO 的5个控制位把由DCORSELx选择的DCO频率分为32等份，间隔大约8% 。
MOD：调制位计数器。选择调制类型，所有的MOD位在FLL运行期间自动调整，无需用户干预。
UCSCTL1
DCORSEL：DCO频率范围选择
DISMOD：调制器禁止使能位。0—使能调制器；1—禁止调制器。
UCSCTL2
FLLD：预分频器（即fDCO分频）。000-1分频，001-2分频，010-4分频，
011-8分频，100-16分频，101-32分频，
110以及111都是备用的，默认为32分频。
FLLN：倍频系数。设置倍频值N，N必须大于0，如果FLLN=0，则N被自动设置为1。
UCSCTL3
SELREF：FLL参考时钟选择。
000-XT1，001-待用，默认为XT1，010-REFO，
101-XT2，其余均为待用，默认为REFO。
FLLREFDIV：FLL参考时钟分频器。000-1分频，001-2分频，010-4分频，
011-8分频，100-12分频，101-16分频，
110以及111都是备用的，默认为16分频。
UCSCTL4
SELA：ACLK时钟源选择。
000-XT1，001-VLO，010-REFO，011-DCO，
100-DCOCLKDIV，101 -XT2有效时为XT2，否则为DCOCLKDIV
110 、111保留以备后来使用。当XT2有效时默认为XT2CLK，否则默认
为DCOCLKDIV
SELS：SMCLK时钟源选择。设置同SELA
SELM：MCLK时钟源选择。设置同SELA
UCSCTL5
DIVPA：ACLK外部有效输出分频000-1分频，001-2分频，010-4分频，
011-8分频，100-16分频，101-32分频，
110以及111都是备用的，默认为32分频。
DIVA：ACLK时钟源分频，设置同DIVPA
DIVS：SMCLK时钟源分频，设置同DIVPA
DIVM：MCLK时钟源分频，设置同DIVPA
UCSCTL6
XT2DRIVE：XT2振荡器电流驱动能力调整
00 最低电流消耗。XT2振荡器工作在4MHz到8MHz …
XT2BYPASS：XT2旁路选择 0-XT2来源于内部时钟（使用外部晶振）
1-XT2来源于外部引脚输入（旁路模式）
XT2OFF：关闭XT2振荡器
0 -当XT2引脚被设置为XT2功能且没有被设置位旁路模式时，XT2被打开；
1 -当XT2没有被用作时钟源以及没有用作FLL参考时钟时，XT2被关闭。
XTS：XT1工作模式选择
0-低频模式（XCAP定义XIN和XOUT引脚间的电容）
1-高频模式（XCAP位没有被使用）
XCAP：振荡器负载电容选择
SMCLKOFF：SMCLK关闭控制位 0-SMCLK开 1-SMCLK关闭
XT1OFF：同XT2OFF
UCSCTL7
XT2OFFG：XT2出错时置位，同时OFFIFG也会置位，需要软件清零。
XT1HFOFFG：高频工作模式下XT1出错时置位，同时OFFIFG也会置位，需要软件清零。
XT1LFOFFG：低频工作模式下XT1出错时置位，同时OFFIFG也会置位，需要软件清零。
DCOOFFG：DCO出错时置位，但当DCO=1或31时，也会置位，同时OFFIFG也会置位，需要软件清零。
UCSCTL8
信号请求使能：
0-相应的信号请求禁止 1-相应的信号请求允许
UCSCTL9
XT1、XT2旁路模式输入摇摆电平（范围）必须被设置
0-输入范围0~DVCC
1-输入范围0~DVIO
3.4实验总结
实验一：将MCLK和SMCLK配置为REFOCLK、VLOCLK(需要示波器测量)
/* REFOCLK和VLOCLK是芯片默认提供的，只要芯片正常工作，这两个时钟就会正常工作，因此，该时钟配置非常简单，只需要修改UCSCTL4，将SELS和SELM配置为对应的选项VLOCLK或者REFOCLK即可*/
#include
void main(void){
WDTCTL = WDTPW+WDTHOLD;
P1SEL |= BIT0;//声明有特殊功能，将不被用作普通I/O
P1DIR |= BIT0;//ACLK输出端，用来测量ACLK频率，外接频率计测
P2SEL |= BIT2;P2DIR |= BIT2;//SMCLK输出端
P7SEL |= BIT7;P7DIR |= BIT7;//MCLK用输出端
//UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_1|SELM_1; //将SMCLK和MCLK配置为VLOCLK
UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_2|SELM_2; //将SMCLK和MCLK配置为REFOCLK
/* UCSCTL4&(~(SELS_7|SELM_7))这一语句相当于先把SELS和SELM清零*/
while(1);
}
/* UCSCTL0 Control Bits */ //#define RESERVED (0x0001u) /* RESERVED */ //#define RESERVED (0x0002u) /* RESERVED */ //#define RESERVED (0x0004u) /* RESERVED */ #define MOD0 (0x0008u) /* Modulation Bit Counter Bit : 0 */ #define MOD1 (0x0010u) /* Modulation Bit Counter Bit : 1 */ #define MOD2 (0x0020u) /* Modulation Bit Counter Bit : 2 */ #define MOD3 (0x0040u) /* Modulation Bit Counter Bit : 3 */ #define MOD4 (0x0080u) /* Modulation Bit Counter Bit : 4 */ #define DCO0 (0x0100u) /* DCO TAP Bit : 0 */ #define DCO1 (0x0200u) /* DCO TAP Bit : 1 */ #define DCO2 (0x0400u) /* DCO TAP Bit : 2 */ #define DCO3 (0x0800u) /* DCO TAP Bit : 3 */ #define DCO4 (0x1000u) /* DCO TAP Bit : 4 */ //#define RESERVED (0x2000u) /* RESERVED */ //#define RESERVED (0x4000u) /* RESERVED */ //#define RESERVED (0x8000u) /* RESERVED */ /* UCSCTL0 Control Bits */ //#define RESERVED (0x0001u) /* RESERVED */ //#define RESERVED (0x0002u) /* RESERVED */ //#define RESERVED (0x0004u) /* RESERVED */ #define MOD0_L (0x0008u) /* Modulation Bit Counter Bit : 0 */ #define MOD1_L (0x0010u) /* Modulation Bit Counter Bit : 1 */ #define MOD2_L (0x0020u) /* Modulation Bit Counter Bit : 2 */ #define MOD3_L (0x0040u) /* Modulation Bit Counter Bit : 3 */ #define MOD4_L (0x0080u) /* Modulation Bit Counter Bit : 4 */ //#define RESERVED (0x2000u) /* RESERVED */ //#define RESERVED (0x4000u) /* RESERVED */ //#define RESERVED (0x8000u) /* RESERVED */ /* UCSCTL0 Control Bits */ //#define RESERVED (0x0001u) /* RESERVED */ //#define RESERVED (0x0002u) /* RESERVED */ //#define RESERVED (0x0004u) /* RESERVED */ #define DCO0_H (0x0001u) /* DCO TAP Bit : 0 */ #define DCO1_H (0x0002u) /* DCO TAP Bit : 1 */ #define DCO2_H (0x0004u) /* DCO TAP Bit : 2 */ #define DCO3_H (0x0008u) /* DCO TAP Bit : 3 */ #define DCO4_H (0x0010u) /* DCO TAP Bit : 4 */ //#define RESERVED (0x2000u) /* RESERVED */ //#define RESERVED (0x4000u) /* RESERVED */ //#define RESERVED (0x8000u) /* RESERVED */ /* UCSCTL1 Control Bits */ #define DISMOD (0x0001u) /* Disable Modulation */ //#define RESERVED (0x0002u) /* RESERVED */ //#define RESERVED (0x0004u) /* RESERVED */ //#define RESERVED (0x0008u) /* RESERVED */ #define DCORSEL0 (0x0010u) /* DCO Freq. Range Select Bit : 0 */ #define DCORSEL1 (0x0020u) /* DCO Freq. Range Select Bit : 1 */ #define DCORSEL2 (0x0040u) /* DCO Freq. Range Select Bit : 2 */ //#define RESERVED (0x0080u) /* RESERVED */ //#define RESERVED (0x0100u) /* RESERVED */ //#define RESERVED (0x0200u) /* RESERVED */ //#define RESERVED (0x0400u) /* RESERVED */ //#define RESERVED (0x0800u) /* RESERVED */ //#define RESERVED (0x1000u) /* RESERVED */ //#define RESERVED (0x2000u) /* RESERVED */ //#define RESERVED (0x4000u) /* RESERVED */ //#define RESERVED (0x8000u) /* RESERVED */ /* UCSCTL1 Control Bits */ #define DISMOD_L (0x0001u) /* Disable Modulation */ //#define RESERVED (0x0002u) /* RESERVED */ //#define RESERVED (0x0004u) /* RESERVED */ //#define RESERVED (0x0008u) /* RESERVED */ #define DCORSEL0_L (0x0010u) /* DCO Freq. Range Select Bit : 0 */ #define DCORSEL1_L (0x0020u) /* DCO Freq. Range Select Bit : 1 */ #define DCORSEL2_L (0x0040u) /* DCO Freq. Range Select Bit : 2 */ //#define RESERVED (0x0080u) /* RESERVED */ //#define RESERVED (0x0100u) /* RESERVED */ //#define RESERVED (0x0200u) /* RESERVED */ //#define RESERVED (0x0400u) /* RESERVED */ //#define RESERVED (0x0800u) /* RESERVED */ //#define RESERVED (0x1000u) /* RESERVED */ //#define RESERVED (0x2000u) /* RESERVED */ //#define RESERVED (0x4000u) /* RESERVED */ //#define RESERVED (0x8000u) /* RESERVED */ /* UCSCTL1 Control Bits */ //#define RESERVED (0x0002u) /* RESERVED */ //#define RESERVED (0x0004u) /* RESERVED */ //#define RESERVED (0x0008u) /* RESERVED */ //#define RESERVED (0x0080u) /* RESERVED */ //#define RESERVED (0x0100u) /* RESERVED */ //#define RESERVED (0x0200u) /* RESERVED */ //#define RESERVED (0x0400u) /* RESERVED */ //#define RESERVED (0x0800u) /* RESERVED */ //#define RESERVED (0x1000u) /* RESERVED */ //#define RESERVED (0x2000u) /* RESERVED */ //#define RESERVED (0x4000u) /* RESERVED */ //#define RESERVED (0x8000u) /* RESERVED */ #define DCORSEL_0 (0x0000u) /* DCO RSEL 0 */ #define DCORSEL_1 (0x0010u) /* DCO RSEL 1 */ #define DCORSEL_2 (0x0020u) /* DCO RSEL 2 */ #define DCORSEL_3 (0x0030u) /* DCO RSEL 3 */ #define DCORSEL_4 (0x0040u) /* DCO RSEL 4 */ #define DCORSEL_5 (0x0050u) /* DCO RSEL 5 */ #define DCORSEL_6 (0x0060u) /* DCO RSEL 6 */ #define DCORSEL_7 (0x0070u) /* DCO RSEL 7 */ /* UCSCTL2 Control Bits */ #define FLLN0 (0x0001u) /* FLL Multipier Bit : 0 */ #define FLLN1 (0x0002u) /* FLL Multipier Bit : 1 */ #define FLLN2 (0x0004u) /* FLL Multipier Bit : 2 */ #define FLLN3 (0x0008u) /* FLL Multipier Bit : 3 */ #define FLLN4 (0x0010u) /* FLL Multipier Bit : 4 */ #define FLLN5 (0x0020u) /* FLL Multipier Bit : 5 */ #define FLLN6 (0x0040u) /* FLL Multipier Bit : 6 */ #define FLLN7 (0x0080u) /* FLL Multipier Bit : 7 */ #define FLLN8 (0x0100u) /* FLL Multipier Bit : 8 */ #define FLLN9 (0x0200u) /* FLL Multipier Bit : 9 */ //#define RESERVED (0x0400u) /* RESERVED */ //#define RESERVED (0x0800u) /* RESERVED */ #define FLLD0 (0x1000u) /* Loop Divider Bit : 0 */ #define FLLD1 (0x2000u) /* Loop Divider Bit : 1 */ #define FLLD2 (0x4000u) /* Loop Divider Bit : 1 */ //#define RESERVED (0x8000u) /* RESERVED */ /* UCSCTL2 Control Bits */ #define FLLN0_L (0x0001u) /* FLL Multipier Bit : 0 */ #define FLLN1_L (0x0002u) /* FLL Multipier Bit : 1 */ #define FLLN2_L (0x0004u) /* FLL Multipier Bit : 2 */ #define FLLN3_L (0x0008u) /* FLL Multipier Bit : 3 */ #define FLLN4_L (0x0010u) /* FLL Multipier Bit : 4 */ #define FLLN5_L (0x0020u) /* FLL Multipier Bit : 5 */ #define FLLN6_L (0x0040u) /* FLL Multipier Bit : 6 */ #define FLLN7_L (0x0080u) /* FLL Multipier Bit : 7 */ //#define RESERVED (0x0400u) /* RESERVED */ //#define RESERVED (0x0800u) /* RESERVED */ //#define RESERVED (0x8000u) /* RESERVED */ /* UCSCTL2 Control Bits */ #define FLLN8_H (0x0001u) /* FLL Multipier Bit : 8 */ #define FLLN9_H (0x0002u) /* FLL Multipier Bit : 9 */ //#define RESERVED (0x0400u) /* RESERVED */ //#define RESERVED (0x0800u) /* RESERVED */ #define FLLD0_H (0x0010u) /* Loop Divider Bit : 0 */ #define FLLD1_H (0x0020u) /* Loop Divider Bit : 1 */ #define FLLD2_H (0x0040u) /* Loop Divider Bit : 1 */ //#define RESERVED (0x8000u) /* RESERVED */ #define FLLD_0 (0x0000u) /* Multiply Selected Loop Freq. 1 */ #define FLLD_1 (0x1000u) /* Multiply Selected Loop Freq. 2 */ #define FLLD_2 (0x2000u) /* Multiply Selected Loop Freq. 4 */ #define FLLD_3 (0x3000u) /* Multiply Selected Loop Freq. 8 */ #define FLLD_4 (0x4000u) /* Multiply Selected Loop Freq. 16 */ #define FLLD_5 (0x5000u) /* Multiply Selected Loop Freq. 32 */ #define FLLD_6 (0x6000u) /* Multiply Selected Loop Freq. 32 */ #define FLLD_7 (0x7000u) /* Multiply Selected Loop Freq. 32 */ #define FLLD__1 (0x0000u) /* Multiply Selected Loop Freq. By 1 */ #define FLLD__2 (0x1000u) /* Multiply Selected Loop Freq. By 2 */ #define FLLD__4 (0x2000u) /* Multiply Selected Loop Freq. By 4 */ #define FLLD__8 (0x3000u) /* Multiply Selected Loop Freq. By 8 */ #define FLLD__16 (0x4000u) /* Multiply Selected Loop Freq. By 16 */ #define FLLD__32 (0x5000u) /* Multiply Selected Loop Freq. By 32 */ /* UCSCTL3 Control Bits */ #define FLLREFDIV0 (0x0001u) /* Reference Divider Bit : 0 */ #define FLLREFDIV1 (0x0002u) /* Reference Divider Bit : 1 */ #define FLLREFDIV2 (0x0004u) /* Reference Divider Bit : 2 */ //#define RESERVED (0x0008u) /* RESERVED */ #define SELREF0 (0x0010u) /* FLL Reference Clock Select Bit : 0 */ #define SELREF1 (0x0020u) /* FLL Reference Clock Select Bit : 1 */ #define SELREF2 (0x0040u) /* FLL Reference Clock Select Bit : 2 */ //#define RESERVED (0x0080u) /* RESERVED */ //#define RESERVED (0x0100u) /* RESERVED */ //#define RESERVED (0x0200u) /* RESERVED */ //#define RESERVED (0x0400u) /* RESERVED */ //#define RESERVED (0x0800u) /* RESERVED */ //#define RESERVED (0x1000u) /* RESERVED */ //#define RESERVED (0x2000u) /* RESERVED */ //#define RESERVED (0x4000u) /* RESERVED */ //#define RESERVED (0x8000u) /* RESERVED */ /* UCSCTL3 Control Bits */ #define FLLREFDIV0_L (0x0001u) /* Reference Divider Bit : 0 */ #define FLLREFDIV1_L (0x0002u) /* Reference Divider Bit : 1 */ #define FLLREFDIV2_L (0x0004u) /* Reference Divider Bit : 2 */ //#define RESERVED (0x0008u) /* RESERVED */ #define SELREF0_L (0x0010u) /* FLL Reference Clock Select Bit : 0 */ #define SELREF1_L (0x0020u) /* FLL Reference Clock Select Bit : 1 */ #define SELREF2_L (0x0040u) /* FLL Reference Clock Select Bit : 2 */ //#define RESERVED (0x0080u) /* RESERVED */ //#define RESERVED (0x0100u) /* RESERVED */ //#define RESERVED (0x0200u) /* RESERVED */ //#define RESERVED (0x0400u) /* RESERVED */ //#define RESERVED (0x0800u) /* RESERVED */ //#define RESERVED (0x1000u) /* RESERVED */ //#define RESERVED (0x2000u) /* RESERVED */ //#define RESERVED (0x4000u) /* RESERVED */ //#define RESERVED (0x8000u) /* RESERVED */ /* UCSCTL3 Control Bits */ //#define RESERVED (0x0008u) /* RESERVED */ //#define RESERVED (0x0080u) /* RESERVED */ //#define RESERVED (0x0100u) /* RESERVED */ //#define RESERVED (0x0200u) /* RESERVED */ //#define RESERVED (0x0400u) /* RESERVED */ //#define RESERVED (0x0800u) /* RESERVED */ //#define RESERVED (0x1000u) /* RESERVED */ //#define RESERVED (0x2000u) /* RESERVED */ //#define RESERVED (0x4000u) /* RESERVED */ //#define RESERVED (0x8000u) /* RESERVED */ #define FLLREFDIV_0 (0x0000u) /* Reference Divider: f(LFCLK)/1 */ #define FLLREFDIV_1 (0x0001u) /* Reference Divider: f(LFCLK)/2 */ #define FLLREFDIV_2 (0x0002u) /* Reference Divider: f(LFCLK)/4 */ #define FLLREFDIV_3 (0x0003u) /* Reference Divider: f(LFCLK)/8 */ #define FLLREFDIV_4 (0x0004u) /* Reference Divider: f(LFCLK)/12 */ #define FLLREFDIV_5 (0x0005u) /* Reference Divider: f(LFCLK)/16 */ #define FLLREFDIV_6 (0x0006u) /* Reference Divider: f(LFCLK)/16 */ #define FLLREFDIV_7 (0x0007u) /* Reference Divider: f(LFCLK)/16 */ #define FLLREFDIV__1 (0x0000u) /* Reference Divider: f(LFCLK)/1 */ #define FLLREFDIV__2 (0x0001u) /* Reference Divider: f(LFCLK)/2 */ #define FLLREFDIV__4 (0x0002u) /* Reference Divider: f(LFCLK)/4 */ #define FLLREFDIV__8 (0x0003u) /* Reference Divider: f(LFCLK)/8 */ #define FLLREFDIV__12 (0x0004u) /* Reference Divider: f(LFCLK)/12 */ #define FLLREFDIV__16 (0x0005u) /* Reference Divider: f(LFCLK)/16 */ #define SELREF_0 (0x0000u) /* FLL Reference Clock Select 0 */ #define SELREF_1 (0x0010u) /* FLL Reference Clock Select 1 */ #define SELREF_2 (0x0020u) /* FLL Reference Clock Select 2 */ #define SELREF_3 (0x0030u) /* FLL Reference Clock Select 3 */ #define SELREF_4 (0x0040u) /* FLL Reference Clock Select 4 */ #define SELREF_5 (0x0050u) /* FLL Reference Clock Select 5 */ #define SELREF_6 (0x0060u) /* FLL Reference Clock Select 6 */ #define SELREF_7 (0x0070u) /* FLL Reference Clock Select 7 */ #define SELREF__XT1CLK (0x0000u) /* Multiply Selected Loop Freq. By XT1CLK */ #define SELREF__REFOCLK (0x0020u) /* Multiply Selected Loop Freq. By REFOCLK */ #define SELREF__XT2CLK (0x0050u) /* Multiply Selected Loop Freq. By XT2CLK */ /* UCSCTL4 Control Bits */ #define SELM0 (0x0001u) /* MCLK Source Select Bit: 0 */ #define SELM1 (0x0002u) /* MCLK Source Select Bit: 1 */ #define SELM2 (0x0004u) /* MCLK Source Select Bit: 2 */ //#define RESERVED (0x0008u) /* RESERVED */ #define SELS0 (0x0010u) /* SMCLK Source Select Bit: 0 */ #define SELS1 (0x0020u) /* SMCLK Source Select Bit: 1 */ #define SELS2 (0x0040u) /* SMCLK Source Select Bit: 2 */ //#define RESERVED (0x0080u) /* RESERVED */ #define SELA0 (0x0100u) /* ACLK Source Select Bit: 0 */ #define SELA1 (0x0200u) /* ACLK Source Select Bit: 1 */ #define SELA2 (0x0400u) /* ACLK Source Select Bit: 2 */ //#define RESERVED (0x0800u) /* RESERVED */ //#define RESERVED (0x1000u) /* RESERVED */ //#define RESERVED (0x2000u) /* RESERVED */ //#define RESERVED (0x4000u) /* RESERVED */ //#define RESERVED (0x8000u) /* RESERVED */ /* UCSCTL4 Control Bits */ #define SELM0_L (0x0001u) /* MCLK Source Select Bit: 0 */ #define SELM1_L (0x0002u) /* MCLK Source Select Bit: 1 */ #define SELM2_L (0x0004u) /* MCLK Source Select Bit: 2 */ //#define RESERVED (0x0008u) /* RESERVED */ #define SELS0_L (0x0010u) /* SMCLK Source Select Bit: 0 */ #define SELS1_L (0x0020u) /* SMCLK Source Select Bit: 1 */ #define SELS2_L (0x0040u) /* SMCLK Source Select Bit: 2 */ //#define RESERVED (0x0080u) /* RESERVED */ //#define RESERVED (0x0800u) /* RESERVED */ //#define RESERVED (0x1000u) /* RESERVED */ //#define RESERVED (0x2000u) /* RESERVED */ //#define RESERVED (0x4000u) /* RESERVED */ //#define RESERVED (0x8000u) /* RESERVED */ /* UCSCTL4 Control Bits */ //#define RESERVED (0x0008u) /* RESERVED */ //#define RESERVED (0x0080u) /* RESERVED */ #define SELA0_H (0x0001u) /* ACLK Source Select Bit: 0 */ #define SELA1_H (0x0002u) /* ACLK Source Select Bit: 1 */ #define SELA2_H (0x0004u) /* ACLK Source Select Bit: 2 */ //#define RESERVED (0x0800u) /* RESERVED */ //#define RESERVED (0x1000u) /* RESERVED */ //#define RESERVED (0x2000u) /* RESERVED */ //#define RESERVED (0x4000u) /* RESERVED */ //#define RESERVED (0x8000u) /* RESERVED */ #define SELM_0 (0x0000u) /* MCLK Source Select 0 */ #define SELM_1 (0x0001u) /* MCLK Source Select 1 */ #define SELM_2 (0x0002u) /* MCLK Source Select 2 */ #define SELM_3 (0x0003u) /* MCLK Source Select 3 */ #define SELM_4 (0x0004u) /* MCLK Source Select 4 */ #define SELM_5 (0x0005u) /* MCLK Source Select 5 */ #define SELM_6 (0x0006u) /* MCLK Source Select 6 */ #define SELM_7 (0x0007u) /* MCLK Source Select 7 */ #define SELM__XT1CLK (0x0000u) /* MCLK Source Select XT1CLK */ #define SELM__VLOCLK (0x0001u) /* MCLK Source Select VLOCLK */ #define SELM__REFOCLK (0x0002u) /* MCLK Source Select REFOCLK */ #define SELM__DCOCLK (0x0003u) /* MCLK Source Select DCOCLK */ #define SELM__DCOCLKDIV (0x0004u) /* MCLK Source Select DCOCLKDIV */ #define SELM__XT2CLK (0x0005u) /* MCLK Source Select XT2CLK */ #define SELS_0 (0x0000u) /* SMCLK Source Select 0 */ #define SELS_1 (0x0010u) /* SMCLK Source Select 1 */ #define SELS_2 (0x0020u) /* SMCLK Source Select 2 */ #define SELS_3 (0x0030u) /* SMCLK Source Select 3 */ #define SELS_4 (0x0040u) /* SMCLK Source Select 4 */ #define SELS_5 (0x0050u) /* SMCLK Source Select 5 */ #define SELS_6 (0x0060u) /* SMCLK Source Select 6 */ #define SELS_7 (0x0070u) /* SMCLK Source Select 7 */ #define SELS__XT1CLK (0x0000u) /* SMCLK Source Select XT1CLK */ #define SELS__VLOCLK (0x0010u) /* SMCLK Source Select VLOCLK */ #define SELS__REFOCLK (0x0020u) /* SMCLK Source Select REFOCLK */ #define SELS__DCOCLK (0x0030u) /* SMCLK Source Select DCOCLK */ #define SELS__DCOCLKDIV (0x0040u) /* SMCLK Source Select DCOCLKDIV */ #define SELS__XT2CLK (0x0050u) /* SMCLK Source Select XT2CLK */ #define SELA_0 (0x0000u) /* ACLK Source Select 0 */ #define SELA_1 (0x0100u) /* ACLK Source Select 1 */ #define SELA_2 (0x0200u) /* ACLK Source Select 2 */ #define SELA_3 (0x0300u) /* ACLK Source Select 3 */ #define SELA_4 (0x0400u) /* ACLK Source Select 4 */ #define SELA_5 (0x0500u) /* ACLK Source Select 5 */ #define SELA_6 (0x0600u) /* ACLK Source Select 6 */ #define SELA_7 (0x0700u) /* ACLK Source Select 7 */ #define SELA__XT1CLK (0x0000u) /* ACLK Source Select XT1CLK */ #define SELA__VLOCLK (0x0100u) /* ACLK Source Select VLOCLK */ #define SELA__REFOCLK (0x0200u) /* ACLK Source Select REFOCLK */ #define SELA__DCOCLK (0x0300u) /* ACLK Source Select DCOCLK */ #define SELA__DCOCLKDIV (0x0400u) /* ACLK Source Select DCOCLKDIV */ #define SELA__XT2CLK (0x0500u) /* ACLK Source Select XT2CLK */ /* UCSCTL5 Control Bits */ #define DIVM0 (0x0001u) /* MCLK Divider Bit: 0 */ #define DIVM1 (0x0002u) /* MCLK Divider Bit: 1 */ #define DIVM2 (0x0004u) /* MCLK Divider Bit: 2 */ //#define RESERVED (0x0008u) /* RESERVED */ #define DIVS0 (0x0010u) /* SMCLK Divider Bit: 0 */ #define DIVS1 (0x0020u) /* SMCLK Divider Bit: 1 */ #define DIVS2 (0x0040u) /* SMCLK Divider Bit: 2 */ //#define RESERVED (0x0080u) /* RESERVED */ #define DIVA0 (0x0100u) /* ACLK Divider Bit: 0 */ #define DIVA1 (0x0200u) /* ACLK Divider Bit: 1 */ #define DIVA2 (0x0400u) /* ACLK Divider Bit: 2 */ //#define RESERVED (0x0800u) /* RESERVED */ #define DIVPA0 (0x1000u) /* ACLK from Pin Divider Bit: 0 */ #define DIVPA1 (0x2000u) /* ACLK from Pin Divider Bit: 1 */ #define DIVPA2 (0x4000u) /* ACLK from Pin Divider Bit: 2 */ //#define RESERVED (0x8000u) /* RESERVED */ /* UCSCTL5 Control Bits */ #define DIVM0_L (0x0001u) /* MCLK Divider Bit: 0 */ #define DIVM1_L (0x0002u) /* MCLK Divider Bit: 1 */ #define DIVM2_L (0x0004u) /* MCLK Divider Bit: 2 */ //#define RESERVED (0x0008u) /* RESERVED */ #define DIVS0_L (0x0010u) /* SMCLK Divider Bit: 0 */ #define DIVS1_L (0x0020u) /* SMCLK Divider Bit: 1 */ #define DIVS2_L (0x0040u) /* SMCLK Divider Bit: 2 */ //#define RESERVED (0x0080u) /* RESERVED */ //#define RESERVED (0x0800u) /* RESERVED */ //#define RESERVED (0x8000u) /* RESERVED */ /* UCSCTL5 Control Bits */ //#define RESERVED (0x0008u) /* RESERVED */ //#define RESERVED (0x0080u) /* RESERVED */ #define DIVA0_H (0x0001u) /* ACLK Divider Bit: 0 */ #define DIVA1_H (0x0002u) /* ACLK Divider Bit: 1 */ #define DIVA2_H (0x0004u) /* ACLK Divider Bit: 2 */ //#define RESERVED (0x0800u) /* RESERVED */ #define DIVPA0_H (0x0010u) /* ACLK from Pin Divider Bit: 0 */ #define DIVPA1_H (0x0020u) /* ACLK from Pin Divider Bit: 1 */ #define DIVPA2_H (0x0040u) /* ACLK from Pin Divider Bit: 2 */ //#define RESERVED (0x8000u) /* RESERVED */ #define DIVM_0 (0x0000u) /* MCLK Source Divider 0 */ #define DIVM_1 (0x0001u) /* MCLK Source Divider 1 */ #define DIVM_2 (0x0002u) /* MCLK Source Divider 2 */ #define DIVM_3 (0x0003u) /* MCLK Source Divider 3 */ #define DIVM_4 (0x0004u) /* MCLK Source Divider 4 */ #define DIVM_5 (0x0005u) /* MCLK Source Divider 5 */ #define DIVM_6 (0x0006u) /* MCLK Source Divider 6 */ #define DIVM_7 (0x0007u) /* MCLK Source Divider 7 */ #define DIVM__1 (0x0000u) /* MCLK Source Divider f(MCLK)/1 */ #define DIVM__2 (0x0001u) /* MCLK Source Divider f(MCLK)/2 */ #define DIVM__4 (0x0002u) /* MCLK Source Divider f(MCLK)/4 */ #define DIVM__8 (0x0003u) /* MCLK Source Divider f(MCLK)/8 */ #define DIVM__16 (0x0004u) /* MCLK Source Divider f(MCLK)/16 */ #define DIVM__32 (0x0005u) /* MCLK Source Divider f(MCLK)/32 */ #define DIVS_0 (0x0000u) /* SMCLK Source Divider 0 */ #define DIVS_1 (0x0010u) /* SMCLK Source Divider 1 */ #define DIVS_2 (0x0020u) /* SMCLK Source Divider 2 */ #define DIVS_3 (0x0030u) /* SMCLK Source Divider 3 */ #define DIVS_4 (0x0040u) /* SMCLK Source Divider 4 */ #define DIVS_5 (0x0050u) /* SMCLK Source Divider 5 */ #define DIVS_6 (0x0060u) /* SMCLK Source Divider 6 */ #define DIVS_7 (0x0070u) /* SMCLK Source Divider 7 */ #define DIVS__1 (0x0000u) /* SMCLK Source Divider f(SMCLK)/1 */ #define DIVS__2 (0x0010u) /* SMCLK Source Divider f(SMCLK)/2 */ #define DIVS__4 (0x0020u) /* SMCLK Source Divider f(SMCLK)/4 */ #define DIVS__8 (0x0030u) /* SMCLK Source Divider f(SMCLK)/8 */ #define DIVS__16 (0x0040u) /* SMCLK Source Divider f(SMCLK)/16 */ #define DIVS__32 (0x0050u) /* SMCLK Source Divider f(SMCLK)/32 */ #define DIVA_0 (0x0000u) /* ACLK Source Divider 0 */ #define DIVA_1 (0x0100u) /* ACLK Source Divider 1 */ #define DIVA_2 (0x0200u) /* ACLK Source Divider 2 */ #define DIVA_3 (0x0300u) /* ACLK Source Divider 3 */ #define DIVA_4 (0x0400u) /* ACLK Source Divider 4 */ #define DIVA_5 (0x0500u) /* ACLK Source Divider 5 */ #define DIVA_6 (0x0600u) /* ACLK Source Divider 6 */ #define DIVA_7 (0x0700u) /* ACLK Source Divider 7 */ #define DIVA__1 (0x0000u) /* ACLK Source Divider f(ACLK)/1 */ #define DIVA__2 (0x0100u) /* ACLK Source Divider f(ACLK)/2 */ #define DIVA__4 (0x0200u) /* ACLK Source Divider f(ACLK)/4 */ #define DIVA__8 (0x0300u) /* ACLK Source Divider f(ACLK)/8 */ #define DIVA__16 (0x0400u) /* ACLK Source Divider f(ACLK)/16 */ #define DIVA__32 (0x0500u) /* ACLK Source Divider f(ACLK)/32 */ #define DIVPA_0 (0x0000u) /* ACLK from Pin Source Divider 0 */ #define DIVPA_1 (0x1000u) /* ACLK from Pin Source Divider 1 */ #define DIVPA_2 (0x2000u) /* ACLK from Pin Source Divider 2 */ #define DIVPA_3 (0x3000u) /* ACLK from Pin Source Divider 3 */ #define DIVPA_4 (0x4000u) /* ACLK from Pin Source Divider 4 */ #define DIVPA_5 (0x5000u) /* ACLK from Pin Source Divider 5 */ #define DIVPA_6 (0x6000u) /* ACLK from Pin Source Divider 6 */ #define DIVPA_7 (0x7000u) /* ACLK from Pin Source Divider 7 */ #define DIVPA__1 (0x0000u) /* ACLK from Pin Source Divider f(ACLK)/1 */ #define DIVPA__2 (0x1000u) /* ACLK from Pin Source Divider f(ACLK)/2 */ #define DIVPA__4 (0x2000u) /* ACLK from Pin Source Divider f(ACLK)/4 */ #define DIVPA__8 (0x3000u) /* ACLK from Pin Source Divider f(ACLK)/8 */ #define DIVPA__16 (0x4000u) /* ACLK from Pin Source Divider f(ACLK)/16 */ #define DIVPA__32 (0x5000u) /* ACLK from Pin Source Divider f(ACLK)/32 */ /* UCSCTL6 Control Bits */ #define XT1OFF (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */ #define SMCLKOFF (0x0002u) /* SMCLK Off */ #define XCAP0 (0x0004u) /* XIN/XOUT Cap Bit: 0 */ #define XCAP1 (0x0008u) /* XIN/XOUT Cap Bit: 1 */ #define XT1BYPASS (0x0010u) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ #define XTS (0x0020u) /* 1: Selects high-freq. oscillator */ #define XT1DRIVE0 (0x0040u) /* XT1 Drive Level mode Bit 0 */ #define XT1DRIVE1 (0x0080u) /* XT1 Drive Level mode Bit 1 */ #define XT2OFF (0x0100u) /* High Frequency Oscillator 2 (XT2) disable */ //#define RESERVED (0x0200u) /* RESERVED */ //#define RESERVED (0x0400u) /* RESERVED */ //#define RESERVED (0x0800u) /* RESERVED */ #define XT2BYPASS (0x1000u) /* XT2 bypass mode : 0: internal 1:sourced from external pin */ //#define RESERVED (0x2000u) /* RESERVED */ #define XT2DRIVE0 (0x4000u) /* XT2 Drive Level mode Bit 0 */ #define XT2DRIVE1 (0x8000u) /* XT2 Drive Level mode Bit 1 */ /* UCSCTL6 Control Bits */ #define XT1OFF_L (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */ #define SMCLKOFF_L (0x0002u) /* SMCLK Off */ #define XCAP0_L (0x0004u) /* XIN/XOUT Cap Bit: 0 */ #define XCAP1_L (0x0008u) /* XIN/XOUT Cap Bit: 1 */ #define XT1BYPASS_L (0x0010u) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ #define XTS_L (0x0020u) /* 1: Selects high-freq. oscillator */ #define XT1DRIVE0_L (0x0040u) /* XT1 Drive Level mode Bit 0 */ #define XT1DRIVE1_L (0x0080u) /* XT1 Drive Level mode Bit 1 */ //#define RESERVED (0x0200u) /* RESERVED */ //#define RESERVED (0x0400u) /* RESERVED */ //#define RESERVED (0x0800u) /* RESERVED */ //#define RESERVED (0x2000u) /* RESERVED */ /* UCSCTL6 Control Bits */ #define XT2OFF_H (0x0001u) /* High Frequency Oscillator 2 (XT2) disable */ //#define RESERVED (0x0200u) /* RESERVED */ //#define RESERVED (0x0400u) /* RESERVED */ //#define RESERVED (0x0800u) /* RESERVED */ #define XT2BYPASS_H (0x0010u) /* XT2 bypass mode : 0: internal 1:sourced from external pin */ //#define RESERVED (0x2000u) /* RESERVED */ #define XT2DRIVE0_H (0x0040u) /* XT2 Drive Level mode Bit 0 */ #define XT2DRIVE1_H (0x0080u) /* XT2 Drive Level mode Bit 1 */ #define XCAP_0 (0x0000u) /* XIN/XOUT Cap 0 */ #define XCAP_1 (0x0004u) /* XIN/XOUT Cap 1 */ #define XCAP_2 (0x0008u) /* XIN/XOUT Cap 2 */ #define XCAP_3 (0x000Cu) /* XIN/XOUT Cap 3 */ #define XT1DRIVE_0 (0x0000u) /* XT1 Drive Level mode: 0 */ #define XT1DRIVE_1 (0x0040u) /* XT1 Drive Level mode: 1 */ #define XT1DRIVE_2 (0x0080u) /* XT1 Drive Level mode: 2 */ #define XT1DRIVE_3 (0x00C0u) /* XT1 Drive Level mode: 3 */ #define XT2DRIVE_0 (0x0000u) /* XT2 Drive Level mode: 0 */ #define XT2DRIVE_1 (0x4000u) /* XT2 Drive Level mode: 1 */ #define XT2DRIVE_2 (0x8000u) /* XT2 Drive Level mode: 2 */ #define XT2DRIVE_3 (0xC000u) /* XT2 Drive Level mode: 3 */ /* UCSCTL7 Control Bits */ #define DCOFFG (0x0001u) /* DCO Fault Flag */ #define XT1LFOFFG (0x0002u) /* XT1 Low Frequency Oscillator Fault Flag */ //#define RESERVED (0x0004u) /* RESERVED */ #define XT2OFFG (0x0008u) /* High Frequency Oscillator 2 Fault Flag */ //#define RESERVED (0x0010u) /* RESERVED */ //#define RESERVED (0x0020u) /* RESERVED */ //#define RESERVED (0x0040u) /* RESERVED */ //#define RESERVED (0x0080u) /* RESERVED */ //#define RESERVED (0x0100u) /* RESERVED */ //#define RESERVED (0x0200u) /* RESERVED */ //#define RESERVED (0x0400u) /* RESERVED */ //#define RESERVED (0x0800u) /* RESERVED */ //#define RESERVED (0x1000u) /* RESERVED */ //#define RESERVED (0x2000u) /* RESERVED */ //#define RESERVED (0x4000u) /* RESERVED */ //#define RESERVED (0x8000u) /* RESERVED */ /* UCSCTL7 Control Bits */ #define DCOFFG_L (0x0001u) /* DCO Fault Flag */ #define XT1LFOFFG_L (0x0002u) /* XT1 Low Frequency Oscillator Fault Flag */ //#define RESERVED (0x0004u) /* RESERVED */ #define XT2OFFG_L (0x0008u) /* High Frequency Oscillator 2 Fault Flag */ //#define RESERVED (0x0010u) /* RESERVED */ //#define RESERVED (0x0020u) /* RESERVED */ //#define RESERVED (0x0040u) /* RESERVED */ //#define RESERVED (0x0080u) /* RESERVED */ //#define RESERVED (0x0100u) /* RESERVED */ //#define RESERVED (0x0200u) /* RESERVED */ //#define RESERVED (0x0400u) /* RESERVED */ //#define RESERVED (0x0800u) /* RESERVED */ //#define RESERVED (0x1000u) /* RESERVED */ //#define RESERVED (0x2000u) /* RESERVED */ //#define RESERVED (0x4000u) /* RESERVED */ //#define RESERVED (0x8000u) /* RESERVED */ /* UCSCTL7 Control Bits */ //#define RESERVED (0x0004u) /* RESERVED */ //#define RESERVED (0x0010u) /* RESERVED */ //#define RESERVED (0x0020u) /* RESERVED */ //#define RESERVED (0x0040u) /* RESERVED */ //#define RESERVED (0x0080u) /* RESERVED */ //#define RESERVED (0x0100u) /* RESERVED */ //#define RESERVED (0x0200u) /* RESERVED */ //#define RESERVED (0x0400u) /* RESERVED */ //#define RESERVED (0x0800u) /* RESERVED */ //#define RESERVED (0x1000u) /* RESERVED */ //#define RESERVED (0x2000u) /* RESERVED */ //#define RESERVED (0x4000u) /* RESERVED */ //#define RESERVED (0x8000u) /* RESERVED */ /* UCSCTL8 Control Bits */ #define ACLKREQEN (0x0001u) /* ACLK Clock Request Enable */ #define MCLKREQEN (0x0002u) /* MCLK Clock Request Enable */ #define SMCLKREQEN (0x0004u) /* SMCLK Clock Request Enable */ #define MODOSCREQEN (0x0008u) /* MODOSC Clock Request Enable */ //#define RESERVED (0x0010u) /* RESERVED */ //#define RESERVED (0x0020u) /* RESERVED */ //#define RESERVED (0x0040u) /* RESERVED */ //#define RESERVED (0x0080u) /* RESERVED */ //#define RESERVED (0x0100u) /* RESERVED */ //#define RESERVED (0x0200u) /* RESERVED */ //#define RESERVED (0x0400u) /* RESERVED */ //#define RESERVED (0x0800u) /* RESERVED */ //#define RESERVED (0x1000u) /* RESERVED */ //#define RESERVED (0x2000u) /* RESERVED */ //#define RESERVED (0x4000u) /* RESERVED */ //#define RESERVED (0x8000u) /* RESERVED */ /* UCSCTL8 Control Bits */ #define ACLKREQEN_L (0x0001u) /* ACLK Clock Request Enable */ #define MCLKREQEN_L (0x0002u) /* MCLK Clock Request Enable */ #define SMCLKREQEN_L (0x0004u) /* SMCLK Clock Request Enable */ #define MODOSCREQEN_L (0x0008u) /* MODOSC Clock Request Enable */ //#define RESERVED (0x0010u) /* RESERVED */ //#define RESERVED (0x0020u) /* RESERVED */ //#define RESERVED (0x0040u) /* RESERVED */ //#define RESERVED (0x0080u) /* RESERVED */ //#define RESERVED (0x0100u) /* RESERVED */ //#define RESERVED (0x0200u) /* RESERVED */ //#define RESERVED (0x0400u) /* RESERVED */ //#define RESERVED (0x0800u) /* RESERVED */ //#define RESERVED (0x1000u) /* RESERVED */ //#define RESERVED (0x2000u) /* RESERVED */ //#define RESERVED (0x4000u) /* RESERVED */ //#define RESERVED (0x8000u) /* RESERVED */ /* UCSCTL8 Control Bits */ //#define RESERVED (0x0010u) /* RESERVED */ //#define RESERVED (0x0020u) /* RESERVED */ //#define RESERVED (0x0040u) /* RESERVED */ //#define RESERVED (0x0080u) /* RESERVED */ //#define RESERVED (0x0100u) /* RESERVED */ //#define RESERVED (0x0200u) /* RESERVED */ //#define RESERVED (0x0400u) /* RESERVED */ //#define RESERVED (0x0800u) /* RESERVED */ //#define RESERVED (0x1000u) /* RESERVED */ //#define RESERVED (0x2000u) /* RESERVED */ //#define RESERVED (0x4000u) /* RESERVED */ //#define RESERVED (0x8000u) /* RESERVED */ /************************************************************ * USCI A0 ************************************************************/ #define __MSP430_HAS_USCI_A0__ /* Definition to show that Module is available */ #define __MSP430_BASEADDRESS_USCI_A0__ 0x05C0 #define UCA0CTLW0_ (0x05C0u) /* USCI A0 Control Word Register 0 */ DEFCW( UCA0CTLW0 , UCA0CTLW0_) #define UCA0CTL1 UCA0CTLW0_L /* USCI A0 Control Register 1 */ #define UCA0CTL0 UCA0CTLW0_H /* USCI A0 Control Register 0 */ #define UCA0BRW_ (0x05C6u) /* USCI A0 Baud Word Rate 0 */ DEFCW( UCA0BRW , UCA0BRW_) #define UCA0BR0 UCA0BRW_L /* USCI A0 Baud Rate 0 */ #define UCA0BR1 UCA0BRW_H /* USCI A0 Baud Rate 1 */ #define UCA0MCTL_ (0x05C8u) /* USCI A0 Modulation Control */ DEFC( UCA0MCTL , UCA0MCTL_) #define UCA0STAT_ (0x05CAu) /* USCI A0 Status Register */ DEFC( UCA0STAT , UCA0STAT_) #define UCA0RXBUF_ (0x05CCu) /* USCI A0 Receive Buffer */ READ_ONLY DEFC( UCA0RXBUF , UCA0RXBUF_) #define UCA0TXBUF_ (0x05CEu) /* USCI A0 Transmit Buffer */ DEFC( UCA0TXBUF , UCA0TXBUF_) #define UCA0ABCTL_ (0x05D0u) /* USCI A0 LIN Control */ DEFC( UCA0ABCTL , UCA0ABCTL_) #define UCA0IRCTL_ (0x05D2u) /* USCI A0 IrDA Transmit Control */ DEFCW( UCA0IRCTL , UCA0IRCTL_) #define UCA0IRTCTL UCA0IRCTL_L /* USCI A0 IrDA Transmit Control */ #define UCA0IRRCTL UCA0IRCTL_H /* USCI A0 IrDA Receive Control */ #define UCA0ICTL_ (0x05DCu) /* USCI A0 Interrupt Enable Register */ DEFCW( UCA0ICTL , UCA0ICTL_) #define UCA0IE UCA0ICTL_L /* USCI A0 Interrupt Enable Register */ #define UCA0IFG UCA0ICTL_H /* USCI A0 Interrupt Flags Register */ #define UCA0IV_ (0x05DEu) /* USCI A0 Interrupt Vector Register */ DEFW( UCA0IV , UCA0IV_)